In the telecommunication world, communication is the key word. This is true not only for communication controllers, but also for computing systems, where components are embedded in a memory hierarchy, with each level in the hierarchy consisting of modules of larger capacity, slower access time and cheaper cost per bit.
Today, large and very large scale integration allows the manufacturing of fast random access memories which can conveniently used for the lower level of the hierarchy. However, optimization of the access to primary memory i.e. the main memory is still desirable. There is a considerable gap between the access times between the various levels of the hierarchy.
There are two major considerations for the treatment of input-output I/O device operations. First, the speed factor relates to the fact that the faster I/O devices are at least three orders of magnitude slower than the main storage. When the I/O device is fast and when the information block to transfer is several words long, an approach based on a buffering concept can be used. The I/O device requests an information transfer by specifying the memory address and the block length.
Second, the data format factor relates to the fact that because of the variety of the I/O devices and memory organizations, a logical interface must be inserted to adapt the different data structures of the I/O devices and of the memory.
To improve their intrinsic failure rate and thus the service cost, the memories are provided with an Error Correcting Code (ECC) capability. The number of ECC bits needed to reach a given detection/correction level is roughly a logarithmic function of the numbers of bits which are processed.
For example, to achieve a single error correction and a double error detection, six ECC bits are needed for two data bytes, seven ECC bits are needed for four data bytes and eight ECC bits are needed for eight data bytes. Hence it is more economical to organize the main memory in words of several bytes width, preferably matching the width of the processor data path, in order to save ECC bits. All mid-size to large size computers have a main storage with a width of m bytes. Now, a conventional value for m is 4 or 8. However, the information burst received from or to be sent to an I/O device does not generally start on a word boundary and this leads to a great performance degradation because for each I/O write operation, the memory controller must:
read the target word in memory, PA0 check the ECC bits and correct the error if any, PA0 merge the I/O data in the word, PA0 compute the new ECC bits, PA0 write the new data and new ECC bits in memory. PA0 clocking means which provide k non-overlapping pulse streams (T1, T2) having the same period T, PA0 memory format adapting means comprising:
This sequence, which is called a "Read Modify Write", impairs the performance of the memory.
Another problem results from the fact that the I/O device format width does not generally match the memory width.
All these problems are generally solved by putting the burden on the I/O device. This device usually must have its own buffer providing data which matches the memory width. A further burden is put on the software which must cause all the I/O data transfers to start at an memory word boundary. Otherwise the Read Modify Write performance penalty is to be paid.